16 124 785 livres à l’intérieur 175 langues
2 047 049 livres numériques à l’intérieur 101 langues
Cela ne vous convient pas ? Aucun souci à se faire ! Vous pouvez renvoyer le produit dans les 30 jours
Impossible de faire fausse route avec un bon d’achat. Le destinataire du cadeau peut choisir ce qu'il veut parmi notre sélection.
Politique de retour sous 30 jours
Now a days due to limitations in communication bandwidth there is more demand for compression in applications like multimedia communication, Television, Video Conferencing etc. This can be done by using DWT(Discrete Wavelet Transform) or DCT (Discrete Cosine Transform). DCT has poor reconstructed image when high compression is performed hence DWT is used. This book presents an implementation of DWT using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cascadable for computation of one, or multi-dimensional DWT. Finally comparison of results of Systolic Array architecture and the lifting based architecture is done, which showed that prior is much faster.