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RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Language
English
English
Book
Paperback
This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Descri...
Full description
Libristo code: 18580422
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307 b
307 b
129.73
€
včetně DPH
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This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synt
About the book
Full name
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Author
Stuart Sutherland
Language
English
English
Binding
Book - Paperback
Date of issue
2017
Number of pages
488
EAN
9781546776345
ISBN
1546776346
Libristo code
18580422
Publishers
Createspace Independent Publishing Platform
Weight
643
Dimensions
152 x 229 x 25
